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184-pin DDR SDRAM DIMM

DIMM: twin Inline memory ModuleSDRAM: Synchronous Dynamic arbitrarily AccessMemory, Synchronous to hopeful Clock Edge.

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DDR: dual Data Rate

184-pin DDR DIMMs use two notches on each side come enablecompatibility through both low- and highprofile latched sockets. Notethat the key position is balance out with respect come the center of theDIMM to prevent inserting it backward in the socket. The key notchis positioned come the left, centered, or to the right of the areabetween pins 52 and also 53. This is offered to suggest the I/O voltagefor the DDR DIMM and to protect against installing the wrong form into asocket that could damage the DIMM.

PIN CONFIGURATIONS(Front side / back side)

PINFRONTPINFRONTPINFRONTPINBACKPINBACKPINBACK
1VREF32A562VDD93VSS124VSS154RAS#
2DQ033DQ2463WE#94DQ4125A6155DQ45
3VSS34VSS64DQ4195DQ5126DQ28156VDD
4DQ135DQ2565CAS#96VDD127DQ29157S0#
5DQS036DQS366VSS97DQS9128VDD158S1#
6DQ237A467DQS598DQ6129DQS12159DQS14
7VDD38VDD68DQ4299DQ7130A3160VSS
8DQ339DQ2669DQ43100VSS131DQ30161DQ46
9NC40DQ2770VDD101NC132VSS162DQ47
10NC41A271NC102NC133DQ31163NC
11VSS42VSS72DQ48103NC134CB4164VDD
12DQ843A173DQ49104VDD135CB5165DQ52
13DQ944CB074VSS105DQ12136VDD166DQ53
14DQS145CB175CK2#106DQ13137CK0167NC
15VDD46VDD76CK2107DQS10138CKO#168VDD
16CK47DQS877VDD108VDD139VSS169DQS15
17CK1#48A078DQS6109DQ14140DQS17170DQ54
18VSS49CB279DQ50110DQ15141A10171DQ55
19DQ1050VSS80DQ51111CKE1142CB6172VDD
20DQ1151CB381VSS112VDD143VDD173NC
21CKE052BA182NC113NC144CB7174DQ60
22VDDKEY83DQ56114DQ20KEY175DQ61
23DQ1653DQ3284DQ57115A12145VSS176VSS
24DQ1754VDD85VDD116VSS146DQ36177DQS16
25DQS255DQ3386DQS7117DQ21147DQ37178DQ62
26VSS56DQS487DQ58118A11148VDD179DQ63
27A957DQ3488DQ59119DQS11149DQS13180VDD
28DQ1858VSS89VSS120VDD150DQ38181SA0
29A759BA090NC121DQ22151DQ39182SA1
30VDD60DQ3591SDA122A8152VSS183SA2
31DQ1961DQ4092SCL123DQ23153DQ44184VDDSPD

PIN DESCRIPTION

PINNAME FUNCTION
A0-A11Address intake (Multiplexed)
BA0~BA1Bank pick Address
DQ0~Q63Data input/output
DQ0~DQS7Data Strobe input/output
CK0, CK0#, CK1, CK1#, CK2, CK2#Clock input
CKE0, CKE1Clock allow input
S0#, S1#Chip pick input
RASRow attend to strobe
CASColumn deal with strobe
WEWrite enable
WPWrite protect
VDDPower it is provided (2.5v)
VDDQPower supply for DQS (2.5V)
VSSGround
VREFPower supply because that reference
VDDSPDSerial EEPROM power Supply (2.3V come 3.6V)
SDASerial data I/O
SCLSerial Clock
SA0-SA2Address in EEPROM
VDDIDVDD to know flag
NCNo connection

References

Category:MemoryConnectors